Accommodating workload diversity in chip multiprocessors
This option, while simplifying the problem, is becoming less and less attractive as its performance and power costs keep increasing.
As a result, exploring options that allow the software to have knowledge about the actual latency/power consumption values is critical for future systems.
in 20th International Symposium on Computer Architecture, May 1993.
Transactional memory: Architectural support for lock-free data structures,.
Second, we study the benefits of varying the frequencies on a subset of the cores to increase EDP savings.
We propose and evaluate integer linear programming based thread mapping schemes in both studies.
Class meets MW 5- in CSE 4217 Schedule: Heterogeneous Cores: Conservation Cores: Reducing the Energy of Mature Computations Ganesh Venkatesh, Jack Sampson, Nathan Goulding, Saturnino Garcia, Vladyslav Bryksin, Jose Lugo-Martinez, Steven Swanson, Michael Bedford Taylor.
In proceedings of the Fifteenth International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS 2010), March 2010 PDF Dynamic Heterogeneity: "Composable Lightweight Processors" C.
Using worst case latency/power assumptions is one option to address process variations.
We propose a novel FCMP architecture named FTPA (flexible tiled processor architecture), which provides an efficient platform for single thread execution.